1. Field of the Invention
The present invention relates to a test apparatus.
2. Description of the Related Art
A test apparatus is employed in order to judge whether or not a semiconductor integrated circuit operates as designed. The test apparatus supplies a predetermined test pattern to a semiconductor integrated circuit (which will simply be referred to as the “DUT (Device Under Test)” hereafter) so as to instruct the DUT to execute processing according to the test pattern. Where the processing performed by the DUT is completed normally, the DUT is judged to be a non-defective product. For example, in a case in which the DUT is memory, data is temporarily written to the DUT, and the data thus written is read out. Furthermore, the data thus read out is compared with the expected value, thereby judging whether or not the data thus read out matches the expected value.
Now, let us consider a case in which flash memory having a multi-bank structure is a test target. FIG. 1 is a block diagram which shows a configuration of NAND flash memory having a multi-bank structure. Flash memory 200a has a two-bank structure including a first bank BANK1 and a second bank BANK2. Each bank includes memory cells 2 and a relief circuit 4. The memory cells 2 of the two banks, i.e., the memory cells 2 of the BANK1 and the BANK2, share the input/output terminals Pio1 through Pio8. It should be noted that the number of input/output terminals Pio1 through Pio8, i.e., the bus width, is described for exemplary purposes only, and can be determined as desired.
The test apparatus writes predetermined data to the memory cell 2 at a predetermined address. In some cases, data cannot be written to the memory cell 2 normally in a single writing operation. Accordingly, the data written or the data erased is compared with the expected value thereof, and retry operations for writing or erasing data are repeatedly executed until the actual data matches the expected value. An upper limit is set on the number of times the retry operation can be repeated. A cell for which the data writing or data erasing cannot be performed normally within the retry limit is judged to be defective.
In order to reduce the test period time, a block containing cells judged to be defective (which will be referred to as “defective cells” hereafter) is eliminated from the subsequent test items. Accordingly, conventional test apparatuses include a logical comparison unit and a fail stack register for each test pin. The logical comparison unit compares the data input via the corresponding test pin with an expected value so as to judge the quality. If the logical comparison unit detects a defective cell even once, the logical comparison unit asserts a flag in the corresponding fail stack register. The test apparatus stores the addresses of the blocks containing the defective cells (which will be referred to as “defective blocks” hereafter), and creates a map of the defective blocks. The addresses registered in the defective block map are not subjected to subsequent tests.
[Patent Document 1]
Japanese Patent Application Laid Open No. 2006-139892
[Patent Document 2]
Japanese Patent Application Laid Open No. 2002-15596
However, as shown in FIG. 1, multi-bank memory has a configuration in which the banks employ common input/output pins. Accordingly, the data output from each bank is input to the same test pin. That is to say, multiple banks are tested by a single logical comparison unit, leading to a problem in that judgment cannot be made regarding which banks contain defective cells. Furthermore, there is a problem in that, in a case in which an operation for generating a test pattern to be written to the flash memory 200a is stopped based upon the value of the fail stack register, when a defective cell is detected at any one of the banks, the testing for the other banks also ends.
The flash memory replaces a defective cell or a defective block with a redundant cell included in the relief circuit 4. However, in a case in which the addresses of the defective cells or the defective blocks (which will be referred to as “defective addresses” hereafter) are stored based upon the judgment results obtained by the logical comparison unit, such an arrangement cannot identify the banks containing the defective cells. This leads to a problem in that the relief circuit 4 cannot perform the appropriate cell replacement.
Such a problem is not restricted to the multi-bank memory, and can occur in an arrangement in which multiple DUTs are connected to a single test pin.